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Since fabrication is still a big issue with memristive technologies, simulation is the most important tool for an early exploration of its capabilities and those of ternary logic which becomes interesting with the arrival of mass manufacturing as it is seen today with transistors. In our project, simulation is used to gain knowledge about the latency and power consumption of ternary arithmetic implementations and memristive storage elements. Several abstraction layers qualify as targets. While analog simulation at circuit level offers the most precise results, it is practically infeasible to perform since it requires much computing power and takes a long time. Hence it is preferable to use a digital simulation model at a higher layer, which does not involve too great deviation from the more exact analog model, but executes within a small fraction of the runtime. Simulation speedups of several magnitudes are achievable here.

Two approaches are being examined in this project to gain data about the energy usage of ternary additions: One at instruction level using an ISA simulator for RISC-V and another one at logic gate level.

The instruction level based power simulation is built on the basis of the official riscv-isa-sim1 reference ISS (instruction set simulator). It originally does not contain any energy usage statistics as this is technology dependent and outside of the scope of ISSs. The main execution loop has been extended to trace relevant instructions based on their opcode, namely those posing explicit additions. For each kind of addition, its average power consumption (based on a representative sample of input vectors) has been determined beforehand for both ternary and binary logic. Each time an addition is encountered in the execution, the arithmetic energy usage is updated. This allows for an easy comparison of power consumption of binary and ternary logic based arithmetic. Since a reference C compiler for RISCV is provided8 and the simulator runs compiled C code with roughly 0.1% of the speed of the host machine, this approach offers fast simulation results with little work required. This does of course imply a trade-off with the accuracy of results, which is why other simulation models are being investigated as well.

To gather power information at logic gate level, the ternary and binary adder were implemented in Verilog. The resulting netlist is then transformed into functionally equivalent C code. The code generation is done via Python, derived from the AST delivered by the parser from pyverilog9. Additional operations have been inserted, updating the energy usage of the adder module each time a signal which is attached to other gates as input changes its value. The energy penalty caused by the signal change is derived as the sum of the energy penaltys for each gate it inputs to. The energy penalty for each gate type is approximated for each of its input ports based on the direction of the value change (whether rising from 0 to 1 or falling from 1 to 0). This approach, although involving higher complexity, is promising to deliver results which are of far greater precision than those based on instruction level simulation.

For more information see our poster presented at the 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS’18). The source code to our tool can be found here.


  1. https://riscv.org/software-tools/risc-v-isa-simulator/
  2. https://github.com/riscv/riscv-gcc
  3. Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015.