Navigation

Language

Steffen Vaas, M. Sc.

Information

2008-2011: Bachelor’s Degree (B.Eng.)

in Electrical Engineering (Nachrichten- und Kommunikationstechnik) at the DHBW Ravensburg

2011-2012: Worked as a development engineer for digital circuit- and FPGA designs at Airbus

2012-2015: Master’s Degree (M.Sc.) in Information and Communication Technology (IuK)

at the Friedrich-Alexander-Universität Erlangen-Nürnberg

2015-now: Research Fellow at the Chair of Computer Architecture

 

Research Interests

  • Deterministic Multi-Core Architectures for Safety-Critical Applications
  • Soft-Core Processors on FPGAs
  • Application-Specific Instruction-Set Processors (ASIP)

 

Selected Publications

Vaas, Steffen; Ulbrich, Peter; Reichenbach, Marc; Fey, Dietmar:
Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands
In: Journal of Signal Processing Systems (2018)  –  DOI: 10.1007/s11265-018-1389-0

 

Vaas, Steffen; Ulbrich, Peter; Reichenbach, Marc; Fey, Dietmar:
The Best of Both: High-performance and Deterministic Real-Time Executive by Application-Specific Multi-Core SoCs
In: HEART (Org.): Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP ’17)
(Conference on Design and Architectures for Signal and Image Processing (DASIP ’17), Dresden, 27.-29. September 2017)

 

Vaas, Steffen; Reichenbach, Marc; Margull, Ulrich; Fey, Dietmar:
The R2-D2 Toolchain – Automated Porting of Safety-Critical Applications to FPGAs
In: Cumplido, René (Org.): Proceedings of ReConFig’ 16
(2016 International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, 30.11.2016 – 02.12.2016)

 

Links to Publishers

Springer Link

IEEE Xplore